Embodiments of the invention relate to electrostatic discharge (ESD) protection, and in particular, a tie-off circuit with output node isolation for protection from ESD.
ESD events may create extremely high voltages/currents that have the potential to destroy integrated circuits (ICs) by driving current into (or drawing current from) the decoupling/parasitic capacitance in the IC chip. ESD protection structures are used to protect Field Effect Transistor (FET) gate oxide and source/drain diffusions that are directly connected to a pad in the Input/Output (I/O) circuits by absorbing/shunting the majority of the ESD pulse.
Technology scaling has enabled performance improvement, density increase and energy reduction, but it has also resulted in degradation of device ESD tolerance. The FET gate oxide breakdown voltage has been steadily decreasing due to reduction in oxide thickness, and the FET source/drain diffusion breakdown voltage has also been decreasing due to higher substrate doping density. Although I/O circuits may use slightly thicker FET gate oxide and lower substrate doping density to mitigate this ESD tolerance degradation, internal circuits use increasingly thinner gate oxide and higher substrate doping density to reap the benefits of technology scaling. Both the FET gate oxide and source/drain diffusion breakdown voltage of internal circuits have decreased.